The invention relates to a vertical MOS filed effect transistor in a semiconductor substrate and a method for producing such a transistor.
The requirement for higher integration density in integrated circuits signifies a reduction in gate length, in particular for field effect transistors. With gate lengths of, for example, 0.5 to 0.2 xcexcm and less, that leads to a sharp increase in short-channel effects, for example:
1) short-channel effect: a stronger influence of space-charge zones of source and drain regions causes a reduction in spatial voltage Uth;
2) narrow-width effect: a proportion of channel edge regions with a radial space-charge zone, which rises in relation to the channel width, leads to an increase in Uth; and
3) punch-through effect: an overlap, occurring for relatively small gate lengths, of the space-charge zones running out from the drain and source regions into the channel causes an increasing reduction in a potential barrier in the channel. As a result, there is a drastic rise in leakage currents below a threshold voltage, as well as a poorer on/off current ratio. A gate oxide thickness must be reduced in order to keep a leakage current density low. In turn, that has a negative influence on dielectric strength, service life and current carrying capacity of the transistor.
Vertical field effect transistors are used in order to avoid disadvantageous short-channel effects despite high integration density, that is to say the channel is vertically disposed relative to the substrate surface. That permits longer gate lengths without increasing a horizontal space requirement. One example of such a vertical transistor is a so-called surrounding gate transistor, in which a vertical channel is surrounded on all sides by a gate. Such an SGT transistor is described in an article entitled: A Surrounding Gate Transistor(SGT) Cell for 64/256 Mbit DRAMs, by K. Sunoushi et al. in IEDM 98-23, 2.1.1. In that case, the gate controls all four sides of the channel. A disadvantage of that concept is a low mobility of the charge carriers in the channel, which worsens electric properties of the transistor.
As a rule, in an integrated circuit there is a need for transistors having various electric properties, that is to say it is necessary, for example, to produce transistors having various channel lengths. Known methods of production for such vertical transistors provide the use of an additional mask level for each channel length, and are therefore very expensive.
It is accordingly an object of the invention to provide a vertical field effect transistor with an internal annular gate and a method of production, which overcome the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type, in which the transistor has improved electric properties and in which the method permits the production of transistors of different channel length without the use of additional mask levels.
With the foregoing and other objects in view there is provided, in accordance with the invention, a vertical MOS transistor, comprising a semiconductor substrate having a surface, a depth and a trench extending from the surface into the depth and defining a trench periphery, a trench interior, a trench bottom and a trench wall with lower, middle and upper regions; a drain region formed by a doped region in the semiconductor substrate adjacent the trench bottom and adjacent the lower region of the trench wall entirely over the trench periphery; a source region formed by a doped region of the semiconductor substrate adjacent the trench wall at the upper region of the trench; a channel region formed by a region of the semiconductor substrate adjacent the trench wall at the middle region of the trench; a gate disposed in the trench interior; an upper insulating layer insulating the gate from the source region; a lower insulating layer insulating the gate from the drain region; a gate dielectric insulating the gate from the channel region; and a drain terminal annularly surrounded by the gate, insulated from the gate and extending from the surface to the drain region.
With the objects of the invention in view there is also provided a method for producing a transistor, which comprises producing a trench in a semiconductor substrate, defining a lower trench region, a trench bottom and a trench wall having an upper region and a lower region; producing a protective layer on the trench wall exposing the trench wall in the lower trench region and the trench bottom; producing a drain region by doping the exposed trench wall and the trench bottom, and removing the protective layer; producing a lower insulating layer on the drain region; producing a source region in the upper region of the trench wall by oblique implantation; producing a gate dielectric on the trench wall, and an upper insulating layer on the source region; producing a gate on the trench wall not filling up the trench; producing an insulation on the gate; and exposing the trench bottom and filling the trench with a conducting layer to form a drain terminal.
In the transistor according to the invention, the source, drain and channel are disposed on the side wall of a trench in a semiconductor substrate. The trench walls are insulated, specifically a gate dielectric is disposed on the middle region of the trench wall, and an upper insulating layer and a lower insulating layer are disposed respectively on the upper and lower region, that is to say on the source and drain regions. The gate is accommodated in the interior of the trench, which has a bag-shaped structure. The drain is constructed annularly around the transistor trench and adjoins the trench bottom. The gate does not fill up the entire trench, but annularly surrounds a drain terminal which reaches from the substrate surface as far as the trench bottom. An insulation is provided between the gate and drain terminal.
The source region is preferably formed from two subregions at opposite points on the trench wall, which are electrically connected to one another in a suitable way. Two subregions of the channel are then correspondingly located on opposite trench walls. In the case of a trench of circular cross section, the channel and source can also annularly surround the entire circumference of the trench.
The upper insulating layer and the lower insulating layer preferably have a greater layer thickness than the gate dielectric, with the result that effective insulation is ensured between the gate and source region or drain region, that is to say the gate capacitance is minimized. A further advantage is that the gate-source capacitance and the gate-drain capacitance are independent of lithography, since those insulating layers are produced in a manner which is self-adjusted relative to the source region and/or drain region.
The low space requirement of the gate electrode (xe2x89xa71F2, wherein F denotes a minimum feature size) permits a high integration density for such transistors. Since the transistor channel is formed of a monocrystalline substrate, such a transistor has good electric properties, such as a long service life, high dielectric strength and high mobility of the charge carriers.
The method of production for the transistor provides for firstly producing the trench with the aid of a mask with the depth required for the transistor and a preselected cross section, and for producing a protective layer on the trench wall which exposes the trench wall in the lower region, that is to say in the vicinity of the bottom of the trench, and exposes the trench bottom. This part of the trench wall, which is exposed and runs around the entire circumference of the transistor trench, and the trench bottom, are then doped with a dopant which has the conductivity type opposite to that of the semiconductor substrate. As a result, a drain region is produced which runs annularly around the lower region of the trench and adjoins the trench bottom. The protective layer serves as a doping mask. A suitable doping method is, in particular, plasma immersion implantation, or deposition doping. A lower insulating layer is produced on the exposed wall and on the trench bottom. The protective layer, or parts thereof still remaining, are removed.
There follows an oblique implantation in the upper region of the exposed trench wall for the purpose of forming a source region. The implantation angle in combination with the width of the trench determines to what trench depth the trench wall is doped, and thus what channel length (non-implanted middle region of the trench wall) remains. If trenches of prescribed depth and different width are produced on the substrate, it is therefore possible to produce transistors of different channel lengths, without the need for a further mask (for example for a further source implantation or channel implantation).
The source implantation can be performed at the same angle in two opposite parts of the trench wall, and the regions thus produced must then be electrically connected in a suitable way. In the case of a trench of circular cross section, an annular continuous source region can be produced by implantation in all sides of the upper trench wall.
It is preferable to implant oxygen in the upper region of the trench wall simultaneously with the source implantation, in which a suitable dopant is implanted. After the oblique implantation, the gate dielectric and the upper insulating layer are produced. A thermal oxidation is preferably carried out. In this case, the implanted oxygen is then also incorporated, with the result that the upper insulating layer is thicker than the gate oxide.
The gate is produced in the interior of the trench, preferably by depositing a doped polysilicon layer which does not fill up the trench, and subsequent anisotropic etching. An insulating layer is formed on a free surface of the gate. The drain region is exposed on the trench bottom, and the trench is filled up with a conducting layer to form the drain terminal.
It is preferred to use a threefold layer as the protective layer which is formed, in particular, of silicon nitride/silicon oxide/silicon nitride, that is applied to the trench wall and to the trench bottom. The upper nitride layer is then etched anisotropically and selectively, the exposed oxide is subsequently isotropically removed and finally, the nitride is etched isotropically and selectively. A nitride/oxide double layer then remains in the upper and middle regions of the trench wall, and the lower wall region and the trench bottom are exposed.
A gate contact is produced on the substrate surface preferably on only one side of the trench by-masking the region of the later gate contact during the spacer etching of the gate so that a (polysilicon) island remains behind in this case.
The source contact of the substrate surface can be produced, for example, by virtue of the fact that during the doping of the drain region a region of the substrate surface adjoining the trench is simultaneously doped. This region is then connected to the actual source region on the trench wall and can be used as an electric terminal. Furthermore, this region can short-circuit two source regions implanted on opposite parts of the trench wall.
The drain terminal is produced by a self-adjusted process management. Its contact area increases with decreasing channel length (that is to say a larger channel width).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a vertical field effect transistor with an internal annular gate and a method of production, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.